The disclosed embodiments of the present invention relate to accessing a memory device, and more particularly, to a method for managing a multi-channel memory device to have improved channel switch response time and a related memory control system.
Computer technology continues to advance at a remarkable pace, with numerous improvements being made to the performance of both of the processor system and the memory system in a computer system. For example, in response to demands for faster, more efficient computer systems, the processor system may be designed to have higher computing power and operate more quickly for dealing with more tasks. If the operating capability of the memory system fails to meet the bandwidth requirement, the memory system would become a performance bottleneck. Hence, attention has been directed to increasing throughput of the memory system.
A multi-channel memory device may be employed to meet the bandwidth requirement. Taking a dual-channel memory device for example, it has two parallel memory channels operating simultaneously to thereby offer larger data throughput. When the number of memory channels used in the multi-channel memory device is larger, it means the power consumption is higher. Further, the computer system does not always need a large memory bandwidth. When the multi-channel memory device has all of its memory channels active under a condition that the computer system only needs a smaller memory bandwidth, the power utilization may not be optimized. If the computer system is a portable device (e.g., a smartphone) powered by a battery device, the battery life may be shortened due to increased power consumption of the memory system. Thus, there is a need for an innovative design which can effectively manage a multi-channel memory to switch between a low power consumption mode and a high memory bandwidth mode.